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Schematics and Settings
SEII voltage I/O specs
SEII DB-37 master pin-out
SIU Scanning I/O B master pin-out
SIU PHA Logic I/O master pin-out
SIU Scanning I/O A master pin-out
SIU v2.2 Horizontal (X) (Fast) (Line) Scanning Circuitry
SIU v2.2 Vertical (Y) (Slow) (Frame) Scanning Circuitry
SIU v2.2 Video A Input Circuitry
SIU v2.2 Video B/C/D Input Circuitry
SIU v2.2 PHA Input Circuitry
SIU v2.2 Relay Enable and External Enable Circuitry
SIU v2.2 Horizontal/Vertical Blank Logic
SIU v2.1 Horizontal (X) (Fast) (Line) Scanning Circuitry
SIU v2.1 Vertical (Y) (Slow) (Frame) Scanning Circuitry
SIU v2.1 Relay Enable and External Enable Circuitry
SIU v1.1 Horizontal (X) (Fast) (Line) Scanning Circuitry
SIU v1.1 Vertical (Y) (Slow) (Frame) Scanning Circuitry
SIU v1.1 Video A Input Circuitry
SIU v1.1 Relay Enable Circuitry
SIU v1.1 PHA Input Circuitry
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4pi Analysis, Inc.
site maintainer:
JH Cholera
last updated:
July 16, 2011
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Schematics and Settings