1/14 nc 2/15 ADC Deadtime 3/16 Pulse Reject 4/17 Deadtime 5/18 nc 6/19 Fast Channel 7/20 SEM Blanking 8/21 WDS_1 Input 9/22 WDS_2 Input 10/23 WDS_3 Input 11/24 WDS_4 Input 12/25 WDS_5 Input
The external Scanning Interface Unit (SIU) has a female DB-25 rear-panel connector labelled PHA Logic I/O. This connector provides all of the interface signals for your pulse processor. Shown below is the schematic of this connector and the master pin-out table for it. Each signal line has its own ground reference. In the table, the pins are listed as [signal/ground].
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1/14 nc 2/15 ADC Deadtime 3/16 Pulse Reject 4/17 Deadtime 5/18 nc 6/19 Fast Channel 7/20 SEM Blanking 8/21 WDS_1 Input 9/22 WDS_2 Input 10/23 WDS_3 Input 11/24 WDS_4 Input 12/25 WDS_5 Input |